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Reported Question / Answer
Q.) In a VHDL retriggerable edge-triggered one-shot, which condition will not exist when a clock edge occurs?
1)
The counter is zero and we need to keep it at zero.
2)
A trigger edge has occurred and we must load the counter.
3)
The counter is not zero and we need to count down by one.
4)
The shift register is reset.
5)
NULL
Answer :
4
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